A spin-on glass formulation is a liquid, silicon-based composition that can be applied to the surface of a substrate, such as a semiconductor wafer and spun with the wafer to provide a coating, preferably with a level top surface. With this technique, the spin-on glass formulation will preferably fill in any valleys or recessed areas in the surface of the semiconductor wafer that result from the various insulating and conductive regions. The spin-on glass coating is then dried to form a solid layer and subsequently cured at high temperatures to form a hard glassy layer. These silicon-based spin-on glass formulations often comprise polyorganosiloxane polymers, which resist shrinking and cracking when cured.
A number of materials are known to be suitable for use as spin-on glass formulations. For example, U.S. Pat. No. 3,615,943 (Genser), U.S. Pat. 3,832,202 (Ritchie), U.S. Pat. No. 4,798,862 (Wood et al.), U.S. Pat. No. 4,865,649 (Kashiwagi) and EP-A-112,649 each describe spin-on glass coating compositions based on polyorganosiloxanes.
Glassy layers obtained from such formulations (referred to herein also as "spin-on glass layers") have been used for various purposes in the manufacture of electronic devices. For example, they find use as planarizing layers, gettering layers for the removal of undesirable impurities, insulating layers for the isolation of multilayer metallizations, doping vehicles for semiconductive substrates for the incorporation of dopants in underlying semiconductor surfaces and absorption layers for enhancing contrast in photolithography techniques. In most of these applications the glassy layer is a utility layer which is applied temporarily to the semiconductor wafer or other substrates in the manufacture of the electronic devices. The spin-on glass layer is eventually removed from the final product, such as when it is used as a gettering layer, diffusion mask or doping vehicle as described in U.S. Pat. No. 4,619,719.
There are two general process schemes for using spin-on glass layers as planarization layers. One is an etch back process wherein after deposition, the spin-on glass layer is etched back to partially expose an underlying CVD oxide. The spin-on glass material remains in the voids providing a planarized surface. Another CVD oxide is then deposited over this planarized surface. The spin-on glass which remains only fills surface voids in this procedure and does not function as a continuous dielectric layer in the electronic device. The CVD oxide provides the continuous dielectric interlayer for the electronic device. In non-etchback processes, the spin-on glass layer is left in place as a continuous dielectric interlayer and helps serve to isolate multilayer metallizations. These continuous spin-on glass layers typically are encapsulated between two layers of CVD oxide to isolate the spin-on glass since it is vulnerable to attack (etching) in subsequent processing such as etching baths and oxygen plasma etch used to remove photoresists. Ting et al., U.S. Pat. No. 4,885,262, describes a method wherein the spin-on glass layer is encapsulated by an underlying CVD oxide and a modified surface obtained by treating the spin-on glass layer with siliating agents followed by oxygen annealing.
Despite the various formulations, a number of limitations exist with respect to the production and use of conventional spin-on glass compositions. Problems of surface damage from subsequent processing, poor adhesion (detachment) to the substrate and instability (shelf life less than six months) among others, have limited the utility of these compositions. For example, conventional spin-on glass layers provide planarization layers of less than 5,000 .ANG., for lower density (large dimension) semiconductor substrates. Another disadvantage of spin-on glass compositions has been that it is difficult to control the plasma etch rate of the layers produced in etch back processing since they are sensitive to oxygen concentration. A typical etching process uses a plasma such as a mixture of CHF.sub.3 and O.sub.2. When the underlying oxide is exposed, it releases additional oxygen into the plasma, causing a significant increase in the etch rate of the spin-on glass layer. This can result in the formation of recesses and loss of uniformity in the surface. These disadvantages have been addressed by Allman, the applicant herein, in providing spin-on glass compositions comprising crosslinked polyorganosiloxanes having a silane adhesion promoter incorporated therein and at least 30 atomic wt. % carbon. Such compositions are described herein, U.S. Pat. Nos. 5,100,503 and 5,152,834 and copending application Ser. No. 07/582,570, filed Sep. 14, 1990. Despite the performance of these spin-on glass compositions in etch back applications, there is a continuing effort to further improve properties such as crack resistance and resistance to oxygen etching (ashing), particularly for non-etchback applications. When patterning vias into a dielectric layer, a high pressure oxygen plasma is typically used to remove the photoresist which patterns the vias. This oxygen attacks the carbon in the spin-on glass film forming carbon dioxide as a byproduct. A stand alone spin-on glass dielectric layer would be exposed to severe attack causing the film to shrink and crack. Where a spin-on glass dielectric layer is encapsulated with CVD oxide layers, it is still exposed to the oxygen plasma in the via cut. The spin-on glass exposed within the via cut shrinks and pulls away from the opening. This causes a problem in forming contacts through the via in that the sputtered metal is incapable of forming a continuous film from the top to the bottom of the via. The sensitivity of the spin-on glass layer to high pressure oxygen etch requires that non-traditional methods be used to remove the photoresist such as low pressure (less than 100 mTorr) oxygen ashing, wherein the oxygen radicals are more directional, preventing them from reacting with the exposed spin-on- glass layer.
It is desirable to provide a spin-on glass layer which is highly resistant to oxygen ashing. Such a glassy layer will allow precise via cuts when used as a dielectric interlayer for electronic devices, which is essential in high density/large scale integrated circuits.